A disadvantaged impedance load driving circuit which is disclosed in U.S. Pat. No. 4,737,696 will be described hereinafter with reference to FIG. 4.
An input signal is supplied to a non-inverting amplifier 1 and an inverting amplifier 2. A load inductance 3 and a current detecting resistor 4 are connected in series between output terminals of the non-inverting amplifier 1 and the inverting amplifier 2. A load current I.sub.L, flowing through the inductance 3, causes a voltage drop which is proportional to the load current I.sub.L across the current detecting resistor 4. A differential amplifier of a current detecting circuit 5 is supplied voltages from both ends of the current detecting resistor 4 in order to detect the amount of voltage drop. The current detecting circuit 5 generates a load current signal representing a value of the load current I.sub.L, and feeds back this load current signal to both the non-inverting amplifier 1 and the inverting amplifier 2.
FIG. 5 shows exemplary circuit embodiments implementing block diagram portions shown in FIG. 4.
Non-inverting amplifier 1 consists of resistors 11, 13 and 14, an operational amplifier 12 and a constant voltage supply 15. Inverting amplifier 2 consists of resistors 21 and 22, an operational amplifier 23 and a constant voltage supply 24. The inductance 3 and the current detecting resistor 4 are connected in series between the output terminals of the operational amplifiers 12 and 23.
The current detecting circuit 5 consists of a differential amplifier 5a comprising resistors 51 to 54, a constant voltage supply 55 and an operational amplifier 56 and further consists of an output inverting circuit 5b receiving an output from the differential amplifier 5a and comprising resistors 57 and 58, an operational amplifier 5g and a constant voltage supply 60. In addition, the output of the differential amplifier 5a is also fed back through the resistor 22 to an inverting terminal of the operational amplifier 23. The output of the output inverting circuit 5b is supplied through the resistor 14 to an inverting terminal of the operational amplifier 12.
In the above disadvantaged approach, a feed-back loop consisting of the differential amplifier 5a and inverting amplifier 2 operates such that an output voltage of the operational amplifier 56 is fed as an input signal to the operational amplifier 23 to be amplified by an inverting amplifier gain (-R.sub.4 /R.sub.3) which is determined by a value R.sub.3 of input resistor 21 and a value R.sub.4 of feed back resistor 22. In further discussing the current detecting circuit 5, the value R of the feedback resistor 57 is set to be equal to the value R of the input resistor 58 so that an output signal from the output inverting circuit 5b is equal to but inverted in comparison to an output signal from the differential amplifier 5a. The output signal from the output inverting circuit 5b is fed as an input signal to the non-inverting amplifier 12 to be amplified by a non-inverting gain (1+R.sub.2 /R.sub.1) which is determined by a value R.sub.1 of input resistor 13 and a value R.sub.2 of feedback resistor 14.
Assuming, in the disadvantaged embodiment being described, that a resistance value Rc of the current detecting resistor 4 is set to be much smaller than a resistance value R of input resistors 51 and 52 of the differential amplifier (i.e., Rc&lt;&lt;R), then a current I.sub.L fed through the load inductance 3 is substantially equal to a current fed through the current detecting resistor 4. Accordingly, as shown in FIGS. 6(A) and 6(C), a level of current IL through load inductance 3 is proportional to the input signal being supplied to the input terminal and is independent of a characteristic of the load inductance 3. In other words, since the load driving circuit drives the load inductance 3 as current driving, the load driving circuit has advantages in that the current fed through the load inductance 3 is independent of the characteristics of the load impedance, and a power voltage is utilized efficiently.
While the output currents of the non-inverting amplifier 1 and the inverting amplifier 2 are controlled as described above, the output voltages V.sub.1 and V.sub.2 thereof are not controlled so that when there is a zero input signal and equal output voltages V.sub.1 and V.sub.2 are established (i.e., V.sub.1 =V.sub.2), a no output current condition is established. During such an occurrence, the output voltages V.sub.1 and V.sub.2 saturate to the power source voltage V.sub.cc or the ground level as shown, for example, in FIG. 6(B) with output voltages saturated to the power source voltage Vcc. Furthermore, during times when the input voltage is positive, the output voltage V.sub.1 becomes saturated at a +V.sub.cc level, and the load current is fed according to only a variation of the output voltage V.sub.2. Similarly, during times when the input voltage is negative, the output voltage V.sub.2 becomes saturated at a +V.sub.cc level, and the load current is fed according to only a variation of the output voltage V.sub.1. During times when there is no or a zero input signal, the output voltages V.sub.1 and V.sub.2 both become saturated at a +V.sub.cc level, and accordingly, when an input signal is at a low level the load is driven proximate a non-linear range of the circuit arrangement. Consequently, the above-described circuit arrangement has disadvantages which may result in an inaccurate signal reproduction (e.g., cross over distortion) since the load current level does not respond to the input signal level accurately), an oscillation caused by an instability in the circuit operation, etc.